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K9WAG08U1A K9K8G08U0A K9NBG08U5A
FLASH MEMORY
K9XXG08UXA
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1
K9WAG08U1A K9K8G08U0A K9NBG08U5A
FLASH MEMORY
Document Title 1G x 8 Bit / 2G x 8 Bit / 4G x 8 Bit NAND Flash Memory Revision History
Revision No
0.0 0.1
History
1. Initial issue 1. Leaded part is eliminated 2. tRHW is defined 1.Comment of "Addressing for program operation" is added (p.17) 1. 4GB DSP is added
Draft Date
Nov. 09. 2005 Jan. 10. 2006
Remark
Advance Preliminary
1.0 1.1
Mar.
7. 2006 Final
July 18th 2006
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.
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K9WAG08U1A K9K8G08U0A K9NBG08U5A
FLASH MEMORY
1G x 8 Bit / 2G x 8 Bit / 4G x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number K9K8G08U0A-Y K9WAG08U1A-Y K9WAG08U1A-I K9NBG08U5A-P 2.70 ~ 3.60V X8 52TLGA TSOP1-DSP Vcc Range Organization PKG Type TSOP1
FEATURES
* Voltage Supply - 2.70V ~ 3.60V * Organization - Memory Cell Array : (1G + 32M) x 8bit - Data Register : (2K + 64) x 8bit * Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte * Page Read Operation - Page Size : (2K + 64)Byte - Random Read : 25s(Max.) - Serial Access : 25ns(Min.) * K9NBG08U5A : 50ns(Min.) * Fast Write Cycle Time - Page Program time : 200s(Typ.) - Block Erase Time : 1.5ms(Typ.) * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles(with 1bit/512Byte ECC) - Data Retention : 10 Years * Command Driven Operation * Intelligent Copy-Back with internal 1bit/528Byte EDC * Unique ID for Copyright Protection * Package : - K9K8G08U0A-PCB0/PIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1A-PCB0/PIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1A-ICB0/IIB0 52 - Pin TLGA (12 x 17 / 1.0 mm pitch) - K9NBG08U5A-PCB0/PIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
GENERAL DESCRIPTION
Offered in 1G x 8bit, the K9K8G08U0A is a 8G-bit NAND Flash Memory with spare 256M-bit. Its NAND cell provides the most costeffective solution for the solid state application market. A program operation can be performed in typical 200s on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns(K9NBG08U5A : 50ns) cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K8G08U0As extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K8G08U0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. An ultra high density solution having two 8Gb stacked with two chip selects is also available in standard TSOPI package and another ultra high density solution having two 16Gb TSOPI package stacked with four chip selects is also available in TSOPI-DSP.
3
K9WAG08U1A K9K8G08U0A K9NBG08U5A
PIN CONFIGURATION (TSOP1)
K9K8G08U0A-PCB0/PIB0
N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C
FLASH MEMORY
48-pin TSOP1 Standard Type 12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F
Unit :mm/Inch
0.10 MAX 0.004 #48 ( 0.25 ) 0.010 12.40 0.488 MAX 0.50 0.0197 #24 #25 1.000.05 0.0390.002 0.25 0.010 TYP
+0.075
20.000.20 0.7870.008
0.008-0.001
+0.003
0.20 -0.03
+0.07
#1
12.00 0.472
0.05 0.002 MIN
0.125 0.035
0~8
0.45~0.75 0.018~0.030
( 0.50 ) 0.020
4
+0.003 0.005-0.001
18.400.10 0.7240.004
1.20 0.047MAX
K9WAG08U1A K9K8G08U0A K9NBG08U5A
PIN CONFIGURATION (TSOP1)
K9WAG08U1A-PCB0/PIB0
N.C N.C N.C N.C N.C R/B2 R/B1 RE CE1 CE2 N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C
FLASH MEMORY
48-pin TSOP1 Standard Type 12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F
Unit :mm/Inch
0.10 MAX 0.004 #48 ( 0.25 ) 0.010 12.40 0.488 MAX 0.50 0.0197 #24 #25 1.000.05 0.0390.002 0.25 0.010 TYP
+0.075
20.000.20 0.7870.008
0.008-0.001
+0.003
0.20 -0.03
+0.07
#1
12.00 0.472
0.05 0.002 MIN
0.125 0.035
0~8
0.45~0.75 0.018~0.030
( 0.50 ) 0.020
5
+0.003 0.005-0.001
18.400.10 0.7240.004
1.20 0.047MAX
K9WAG08U1A K9K8G08U0A K9NBG08U5A
FLASH MEMORY
K9WAG08U1A - ICB0 / IIB0
A
NC
B
NC
C
D
E
NC
F
G
H
J
K
NC
L
M
N
NC
NC
7
NC /RE1 Vcc /CE1 /CE2 CLE2 /RE2 R/B1 R/B2 Vss /WP2 IO0-1 IO7-2 IO6-2 IO5-2 Vcc IO4-2 IO3-2 Vss IO2-2 NC NC NC NC
6 5 4 3 2 1
NC NC
IO7-1 IO6-1
IO5-1 IO4-1 Vss
CLE1 Vss
/WE1 /WP1
IO2-1 IO3-1
ALE2 ALE1
IO1-1 IO0-2
/WE2 NC
IO1-2 NC
NC
PACKAGE DIMENSIONS
52-TLGA (measured in millimeters) Top View Bottom View
12.000.10 10.00 1.00 1.00 6 5 4 3 2 1.00 1 1.30
A B
2.00 12.000.10 7
(Datum A)
#A1
1.00
A B C D
(Datum B)
1.00 2.50
12-1.000.05 0.1 M C AB
17.000.10
F G
J K L M N
1.00
H
41-0.700.05
0.1
M C AB
17.000.10
0.10 C
6
1.0(Max.)
Side View
0.50
2.00
1.00 2.50
12.00 17.000.10
E
K9WAG08U1A K9K8G08U0A K9NBG08U5A
PIN CONFIGURATION (TSOP1-DSP)
K9NBG08U5A-PCB0/PIB0
N.C N.C N.C R/B4 R/B3 R/B2 R/B1 RE CE1 CE2 N.C Vcc Vss CE3 CE4 CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
FLASH MEMORY
48-pin TSOP1 Dual Stacked Package 12mm x 20mm
N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C
PACKAGE DIMENSIONS
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220AF
18.80 MAX REF
Unit :mm/Inch
SEATING PLANE -A#48
n Pi
#1 0.13~0.23
12.40 MAX REF
#24 (0.10) A TYP BOTH SIDES BOTTOM TSOP ONLY (0.249) BASIC GAGE PLANE 0.399~0.600 20.000.20 0.02 MIN
#25
0.50 TYP
7
2.35 MAX
#1
(0.10) A
K9WAG08U1A K9K8G08U0A K9NBG08U5A
PIN DESCRIPTION
Pin Name I/O0 ~ I/O7 Pin Function
FLASH MEMORY
DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE The CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE / CE1 control during read operation , refer to 'Page Read' section of Device operation. CHIP ENABLE The CE2 input enables the second K9K8G08U0A READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WRITE PROTECT The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. READY/BUSY OUTPUT The R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. POWER VCC is the power supply for device. GROUND NO CONNECTION Lead is not internally connected.
CLE
ALE
CE / CE1
CE2
RE
WE
WP
R/B / R/B1
Vcc Vss N.C
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. There are two CE pins (CE1 & CE2) in the K9WAG08U1A and four CE pins (CE1 & CE2 & CE3 & CE4) in the K9NBG08U5A. There are two R/B pins (R/B1 & R/B2) in the K9WAG08U1A and four R/B pins (R/B1 & R/B2 & R/B3 & R/B4) in the K9NBG08U5A.
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K9WAG08U1A K9K8G08U0A K9NBG08U5A
Figure 1. K9K8G08U0A Functional Block Diagram
VCC VSS A12 - A30 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders 8,192M + 256M Bit NAND Flash ARRAY
FLASH MEMORY
A0 - A11
(2,048 + 64)Byte x 524,288 Data Register & S/A Y-Gating
Command Command Register I/O Buffers & Latches VCC VSS Output Driver I/0 0
CE RE WE
Control Logic & High Voltage Generator
Global Buffers
I/0 7 CLE ALE WP
Figure 2. K9K8G08U0A Array Organization
1 Block = 64 Pages (128K + 4k) Byte
512K Pages (=8,192 Blocks) 8 bit 2K Bytes 64 Bytes
1 Page = (2K + 64)Bytes 1 Block = (2K + 64)B x 64 Pages = (128K + 4K) Bytes 1 Device = (2K+64)B x 64Pages x 8,192 Blocks = 8,448 Mbits
Page Register
2K Bytes I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle A0 A8 A12 A20 A28 I/O 1 A1 A9 A13 A21 A29 I/O 2 A2 A10 A14 A22 A30 64 Bytes I/O 3 A3 A11 A15 A23 *L
I/O 0 ~ I/O 7
I/O 4 A4 *L A16 A24 *L
I/O 5 A5 *L A17 A25 *L
I/O 6 A6 *L A18 A26 *L
I/O 7 A7 *L A19 A27 *L Column Address Column Address Row Address Row Address
Row Address
NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required.
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K9WAG08U1A K9K8G08U0A K9NBG08U5A
Product Introduction
FLASH MEMORY
The K9K8G08U0A is a 8,448Mbit(8,858,370,048 bit) memory organized as 524,288 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 8,192 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K8G08U0A. The K9K8G08U0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1056M byte physical space requires 31 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K8G08U0A. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased. The K9WAG08U1A is composed of two K9K8G08U0A chips which are selected separately by each CE1 and CE2 and the K9NBG08U5A is composed of four K9K8G08U0A chips which are selected seperately by each CE1, CE2, CE3 and CE4. Therefore, in terms of each CE, the basic operations of K9WAG08U0A and K9NBG08U5A are same with K9K8G08U0A except some AC/DC charateristics.
Table 1. Command Sets
Function Read Read for Copy Back Read ID Reset Page Program Two-Plane Page Program(4) Copy-Back Program Two-Plane Copy-Back Program(4) Block Erase Two-Plane Block Erase Random Data Input(1) Random Data Output(1) Read Status Read EDC Status Chip1 Status Chip2 Status
(3) (3) (2)
1st Cycle 00h 00h 90h FFh 80h 80h---11h 85h 85h---11h 60h 60h---60h 85h 05h 70h 7Bh F1h F2h
2nd Cycle 30h 35h 10h 81h---10h 10h 81h---10h D0h D0h E0h
Acceptable Command during Busy
O
O O O O
NOTE : 1. Random Data Input/Output can be executed in a page. 2. Read EDC Status is only available on Copy Back operation. 3. Interleave-operation between two chips is allowed. It's prohibited to use F1h and F2h commands for other operations except interleave-operation. 4. Any command between 11h and 81h is prohibited except 70h, F1h, F2h and FFh .
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
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K9WAG08U1A K9K8G08U0A K9NBG08U5A
Memory Map
FLASH MEMORY
K9K8G08U0A is arranged in four 2Gb memory planes. Each plane contains 2,048 blocks and 2112 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that two-plane program/erase operations can be executed by dividing the memory array into plane 0~1 or plane 2~3 separately. For example, two-plane program/erase operation into plane 0 and plane 2 is prohibited. That is to say, two-plane program/erase operation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed
Plane 0 (2048 Block)
Plane 1 (2048 Block)
Plane 2 (2048 Block)
Plane 3 (2048 Block)
Block 0 Page 0 Page 1
Block 1 Page 0 Page 1
Block 4096 Page 0 Page 1
Block 4097 Page 0 Page 1
Page 62 Page 63 Block 2 Page 0 Page 1
Page 62 Page 63 Block 3 Page 0 Page 1
Page 62 Page 63 Block 4098 Page 0 Page 1
Page 62 Page 63 Block 4099 Page 0 Page 1
Page 62 Page 63
Page 62 Page 63
Page 62 Page 63
Page 62 Page 63
Block 4092 Page 0 Page 1
Block 4093 Page 0 Page 1
Block 8188 Page 0 Page 1
Block 8189 Page 0 Page 1
Page 62 Page 63 Block 4094 Page 0 Page 1
Page 62 Page 63 Block 4095 Page 0 Page 1
Page 62 Page 63 Block 8190 Page 0 Page 1
Page 62 Page 63 Block 8191 Page 0 Page 1
Page 62 Page 63
2112byte Page Registers
Page 62 Page 63
2112byte Page Registers
Page 62 Page 63
2112byte Page Registers
Page 62 Page 63
2112byte Page Registers
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K9WAG08U1A K9K8G08U0A K9NBG08U5A
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS K9XXG08UXA-XCB0 K9XXG08UXA-XIB0 K9XXG08UXA-XCB0 K9XXG08UXA-XIB0 Symbol VCC VIN VI/O Temperature Under Bias Storage Temperature Short Circuit Current TBIAS TSTG
IOS
FLASH MEMORY
Rating -0.6 to +4.6 -0.6 to +4.6 -0.6 to Vcc+0.3 (<4.6V) -10 to +125 -40 to +125 -65 to +150
5
Unit V
C C
mA
NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9XXG08UXA-XCB0 :TA=0 to 70C, K9XXG08UXA-XIB0:TA=-40 to 85C) Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7 0 Typ. 3.3 0 Max 3.6 0 Unit V V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Page Read with Operating Serial Access Current Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH(1) VIL(1) VOH VOL IOL(R/B) IOH=-400A IOL=2.1mA VOL=0.4V Test Conditions tRC=25ns(K9NBG08U5A: 50ns) CE=VIL, IOUT=0mA CE=VIH, WP=0V/VCC CE=VCC-0.2, WP=0V/VCC VIN=0 to Vcc(max) VOUT=0 to Vcc(max) 0.8xVcc -0.3 2.4 8 20 10 1 100 20 20 Vcc+0.3 0.2xVcc 0.4 mA V A 25 35 mA Min Typ Max Unit
NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, TA=25C. Not 100% tested. 3. The typical value of the K9WAG08U1A's ISB2 is 40A and the maximum value is 200A. 4. The typical value of the K9NBG08U5A's ISB2 is 80A and the maximum value is 400A. 5. The maximum value of K9WAG08U1A-P's ILI and ILO is 40A, the maximum value of K9WAG08U1A-I's ILI and ILO is 20A. 6. The maximum value of K9NBG08U5A's ILI and ILO is 80A.
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K9WAG08U1A K9K8G08U0A K9NBG08U5A
VALID BLOCK
Parameter K9K8G08U0A K9WAG08U1A K9NBG08U5A Symbol NVB NVB NVB Min 8,032 16,064* 32,128* Typ. -
FLASH MEMORY
Max 8,192 16,384* 32,768* Unit Blocks Blocks Blocks
NOTE : 1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC. 3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations. * : Each K9K8G08U0A chip in the K9WAG08U1A and K9NBG08U5A has Maximun 160 invalid blocks.
AC TEST CONDITION
(K9XXG08UXA-XCB0: TA=0 to 70C, K9XXG08UXA-XIB0:TA=-40 to 85C ,K9XXG08UXA: Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load K9XXG08UXA 0V to Vcc 5ns Vcc/2 1 TTL GATE and CL=50pF (K9K8G08U0A-P/K9WAG08U1A-I) 1 TTL GATE and CL=30pF (K9WAG08U1A-P) 1 TTL GATE and CL=30pF (K9NBG08U5A-P)
CAPACITANCE(TA=25C, VCC=3.3V, f=1.0MHz)
Item Input/Output CapaciInput Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max K9K8G08U0A 20 20 K9WAG08U1A* 40 40 K9NBG08U5A 80 80 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested. K9WAG08U1A-IXB0's capacitance(I/O, Input) is 20pF.
MODE SELECTION
CLE H L H L L L X X X X X ALE L H L H L L X X X X(1) X CE L L L L L L X X X X H H X X X X X H X X X X WE RE H H H H H WP X X H H H X X H H L 0V/VCC(2) Read Mode Write Mode Data Input Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect Stand-by Mode Command Input Address Input(5clock) Command Input Address Input(5clock)
NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby.
13
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Program / Erase Characteristics
Parameter Program Time Dummy Busy Time for Two-Plane Page Program Number of Partial Program Cycles Block Erase Time Symbol tPROG tDBSY Nop tBERS Min Typ 200 0.5 1.5
FLASH MEMORY
Max 700 1 4 2 Unit s s cycles ms
NOTE : 1. Typical value is measured at Vcc=3.3V, TA=25C. Not 100% tested. 2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25C temperature.
AC Timing Characteristics for Command / Address / Data Input
Min Parameter CLE Setup Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time Address to Data Loading Time Symbol tCLS(1) tCLH tCS
(1)
Max K9K8G08U0A K9WAG08U1A 12 5 20 5 12 12 5 12 5 25 10 70 K9NBG08U5A K9K8G08U0A K9WAG08U1A ns ns ns ns ns ns ns ns ns ns ns ns Unit
K9NBG08U5A 25 10 35 10 25 25 10 20 10 45 15 70
tCH tWP tALS(1) tALH tDS(1) tDH tWC tWH tADL(2)
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle
14
K9WAG08U1A K9K8G08U0A K9NBG08U5A
AC Characteristics for Operation
Min Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE High to Output hold RE Low to Output hold CE High to Output hold RE High Hold Time Output Hi-Z to RE Low RE High to WE Low WE High to RE Low Device Resetting Time(Read/Program/Erase) Symbol tR tAR tCLR tRR tRP tWB tRC tREA tCEA tRHZ tCHZ tRHOH tRLOH tCOH tREH tIR tRHW tWHR tRST 10 10 20 25 50 15 15 15 0 100 60 K9NBG08U5A K9K8G08U0A K9WAG08U1A 10 10 20 12 25 15 5 15 10 0 100 60 -
FLASH MEMORY
Max K9NBG08U5A 20 K9K8G08U0A K9WAG08U1A 20 100 30 45 100 30 5/10/500
(1)
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
100 20 25 100 30 5/10/500
(1)
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5s.
15
K9WAG08U1A K9K8G08U0A K9NBG08U5A
NAND Flash Technical Notes
Initial Invalid Block(s)
FLASH MEMORY
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
*
Create (or update) Initial Invalid Block(s) Table No Check "FFh" Yes No
Check "FFh" at the column address 2048 of the 1st and 2nd page in the block
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table.
16
K9WAG08U1A K9K8G08U0A K9NBG08U5A
NAND Flash Technical Notes (Continued)
Error in write or read operation
FLASH MEMORY
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode Write Read Erase Failure Program Failure Single Bit Failure
Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Verify ECC -> ECC Correction
ECC
: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ?
No
Program Error
*
Yes Program Completed
*
17
: If program operation results in an error, map out the block including the page in error and copy the target data to another block.
K9WAG08U1A K9K8G08U0A K9NBG08U5A
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Start Write 60h Write Block Address Write D0h Read Status Register
FLASH MEMORY
Read Flow Chart
Start Write 00h Write Address Write 30h Read Data ECC Generation I/O 6 = 1 ? or R/B = 1 ? Yes No No
Erase Error
*
Reclaim the Error
Verify ECC Yes Page Read Completed
No
I/O 0 = 0 ? Yes Erase Completed
*
: If erase operation results in an error, map out the failing block and replace it with another block.
Block Replacement
1st (n-1)th nth (page)
{ {
Block A 1 an error occurs. Buffer memory of the controller. Block B 2
1st (n-1)th nth (page)
* Step1 When an error happens in the nth page of the Block 'A' during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B') * Step3 Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B'. * Step4 Do not erase or program to Block 'A' by creating an 'invalid Block' table or other appropriate scheme.

18
K9WAG08U1A K9K8G08U0A K9NBG08U5A
NAND Flash Technical Notes (Continued)
Copy-Back Operation with EDC & Sector Definition for EDC
FLASH MEMORY
Generally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors. K9K8G08U0A supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes. A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte spare area.
Main Field (2,048 Byte)
Spare Field (64 Byte)
"A" area (1'st sector) 512 Byte
"B" area (2'nd sector) 512 Byte
"C" area (3'rd sector) 512 Byte
"D" area (4'th sector) 512 Byte
"E" area "F" area "G" area "H" area (1'st sector) (2'nd sector) (3'rd sector) (4'th sector) 16 Byte 16 Byte 16 Byte 16 Byte
Table 2. Definition of the 528-Byte Sector
Sector 1'st 528-Byte Sector 2'nd 528-Byte Sector 3'rd 528-Byte Sector 4'th 528-Byte Sector Main Field (Column 0~2,047) Area Name "A" "B" "C" "D" Column Address 0 ~ 511 512 ~ 1,023 1,024 ~ 1,535 1,536 ~ 2,047 Spare Field (Column 2,048~2,111) Area Name "E" "F" "G" "H" Column Address 2,048 ~ 2,063 2,064 ~ 2,079 2,080 ~ 2,095 2,096 ~ 2,111
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0.
Page 63
(64)
:
Page 63
(64)
:
Page 31
(32)
:
Page 31
(1)
:
Page 2 Page 1 Page 0
(3) (2) (1)
Page 2 Page 1 Page 0
(3) (32) (2)
Data register From the LSB page to MSB page DATA IN: Data (1) Data (64)
Data register Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64)
19
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Interleave Page Program
FLASH MEMORY
K9K8G08U0A is composed of two K9F4G08U0As. K9K8G08U0A provides interleaving operation between two K9F4G08U0As. This interleaving page program improves the system throughput almost twice compared to non-interleaving page program. At first, the host issues page program command to one of the K9F4G08U0A chips, say K9F4G08U0A(chip #1). Due to this K9K8G08U0A goes into busy state. During this time, K9F4G08U0A(chip #2) is in ready state. So it can execute the page program command issued by the host. After the execution of page program by K9F4G08U0A(chip #1), it can execute another page program regardless of the K9F4G08U0A(chip #2). Before that the host needs to check the status of K9F4G08U0A(chip #1) by issuing F1h command. Only when the status of K9F4G08U0A(chip #1) becomes ready status, host can issue another page program command. If the K9F4G08U0A(chip #1) is in busy state, the host has to wait for the K9F4G08U0A(chip #1) to get into ready state. Similarly, K9F4G08U0A chip(chip #2) can execute another page program after the completion of the previous program. The host can monitor the status of K9F4G08U0A(chip #2) by issuing F2h command. When the K9F4G08U0A(chip #2) shows ready state, host can issue another page program command to K9F4G08U0A(chip #2). This interleaving algorithm improves the system throughput almost twice. The host can issue page program command to each chip individually. This reduces the time lag for the completion of operation. NOTES : During interleave operations, 70h command is prohibited.
20
Interleave Page Program
Add & Data A30 : Low A30 : High F1h or F2h 10h 10h Command 80h Add & Data
I/OX
80h
another page program on Chip #1
R/ B (#1)
busy of Chip #1
internal only
K9WAG08U1A K9K8G08U0A K9NBG08U5A
R/B
(#2) internal only
busy of Chip #2
R/B
A
B
C
D
21
Status A B C D Operation Chip 1 : Busy, Chip 1 : Busy, Chip 2 : Ready Chip 2 : Busy Chip 1 : Ready, Chip 2 : Busy Chip 1 : Ready, Chip 2 : Ready Status Command / Data F1h 8xh 8xh Cxh Cxh F2h Cxh 8xh 8xh Cxh
State A : Chip #1 is executing a page program operation and chip #2 is in ready state. So the host can issue a page program command to chip #2. State B : Both chip #1 and chip #2 are executing page program operation. State C : Page program on chip #1 is terminated, but page program on chip #2 is still operating. And the system should issue F1h command to detect the status of chip #1. If chip #1 is ready, status I/O6 is "1" and the system can issue another page program command to chip #1. State D : Chip #1 and Chip #2 are ready.
According to the above process, the system can operate page program on chip #1 and chip #2 alternately.
FLASH MEMORY
Interleave Block Erase
Add A30 : Low A30 : High F1h or F2h D0h D0h Command 60h Add
I/OX
60h
another Block Erase on Chip #1
R/ B (#1)
busy of Chip #1
internal only
K9WAG08U1A K9K8G08U0A K9NBG08U5A
R/B
R/B
(#2) internal only
busy of Chip #2
A
B
C
D
22
Status A B C D Operation Chip 1 : Busy, Chip 1 : Busy, Chip 2 : Ready Chip 2 : Busy Chip 1 : Ready, Chip 2 : Busy Chip 1 : Ready, Chip 2 : Ready Status Command / Data F1h 8xh 8xh Cxh Cxh F2h Cxh 8xh 8xh Cxh
State A : Chip #1 is executing a block erase operation, and chip #2 is in ready state. So the host can issue a block erase command to chip #2. State B : Both chip #1 and chip #2 are executing block erase operation. State C : Block erase on chip #1 is terminated, but block erase on chip #2 is still operating. And the system should issue F1h command to detect the status of chip #1. If chip #1 is ready, status I/O6 is "1" and the system can issue another block erase command to chip #1. State D : Chip #1 and Chip #2 are ready.
According to the above process, the system can operate block erase on chip #1 and chip #2 alternately.
FLASH MEMORY
Interleave Two-Plane Page Program
11h 81h Add & Data A30 :Low A30: High A30 :High 10h 80h Add & Data 11h 81h Add & Data 10h
I/OX
80h
Add & Data
A30 : Low
R/B (#1) t DBSY t PROG of chip #1
internal only
internal only
R/B (#2)
t DBSY
tPROG of Chip #2
K9WAG08U1A K9K8G08U0A K9NBG08U5A
R/B
A
B 1 D
I/OX
Command
23 tPROG of Chip #2 C
F1h or F2h*
R/nB (#1)
internal only
R/B (#2)
internal only
R/B
1
FLASH MEMORY
State A : Chip #1 is executing a page program operation, and chip #2 is in ready state. So the host can issue a page program command to chip #2. State B : Both chip #1 and chip #2 are executing page program operation. State C : Page program on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing page program operation. State D : Both chip #1 and chip #2 are ready. Note : *F1h command is required to check the status of chip #1 to issue the next page program command to chip #1. F2h command is required to check the status of chip #2 to issue the next page program command to chip #2. According to the above process, the system can operate two-plane page program on chip #1 and chip #2 alternately.
Interleave Two-Plane Block Erase
I/OX
Add Add Add A30 :High A30 :Low A30 : High 60h 60h D0h 60h Add D0h
60h
A30 : Low
R/B (#1) t BERS of
chip #1
internal only
internal only
K9WAG08U1A K9K8G08U0A K9NBG08U5A
R/B
A
R/B (#2)
t BERS of chip #2
B
1
I/OX
Command
24 tBERS of
chip #2
F1h or F2h*
R/B (#1)
internal only
R/B (#2)
internal only
R/B C D
1
FLASH MEMORY
State A : Chip #1 is executing a block erase operation, and chip #2 is in ready state. So the host can issue a block erase command to chip #2. State B : Both chip #1 and chip #2 are executing block erase operation. State C : Block erase on chip #1 is completed and chip #1 is ready for the next operation. Chip #2 is still executing block erase operation. State D : Both chip #1 and chip #2 are ready. Note : *F1h command is required to check the status of chip #1 to issue the next block erase command to chip #1. F2h command is required to check the status of chip #2 to issue the next block erase command to chip #2. As the above process, the system can operate two-plane block erase on chip #1 and chip #2 alternatively.
K9WAG08U1A K9K8G08U0A K9NBG08U5A
System Interface Using CE don't-care.
FLASH MEMORY
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of -seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.
Figure 4. Program Operation with CE don't-care.
CE don't-care
I/Ox
80h
Address(5Cycles)
Data Input
Data Input
ALE
WE
CE
CLE
10h
tCS CE
tCH CE
tCEA
tREA tWP WE I/O0~7 out RE
Figure 5. Read Operation with CE don't-care.
CE don't-care
CE
RE ALE R/B

tR
I/Ox
WE
00h
Address(5Cycle)
30h
Data Output(serial access)
25

CLE
K9WAG08U1A K9K8G08U0A K9NBG08U5A
NOTE
FLASH MEMORY
DATA ADDRESS Col. Add1 A0~A7 Col. Add2 A8~A11 Row Add1 A12~A19 Row Add2 A20~A27 Row Add3 A28~A30
Device K9K8G08U0A
I/O I/Ox I/O 0 ~ I/O 7
Data In/Out 2,112byte
Command Latch Cycle
CLE tCLS tCS CE tCLH tCH
tWP WE
tALS ALE tDS I/Ox
tALH
tDH
Command
Address Latch Cycle
tCLS CLE tCS tWC CE tWC tWC tWC
tWP WE tALS ALE tDS I/Ox tDH tWH tALH
tWP tALS tALH tWH
tWP tALS tWH tALH
tWP tALS tWH tALH tALS tALH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Col. Add1
Col. Add2
Row Add1
Row Add2
Row Add3
26
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Input Data Latch Cycle
tCLH
FLASH MEMORY
CLE
tCH CE
tWC ALE tALS WE tDS I/Ox
tWH tDH
tDS
tDH
tWP
tWP
tWP tDH tDS
DIN 0 DIN 1 DIN final tRC
* Serial access Cycle after Read(CLE=L, WE=H, ALE=L)
CE tREA RE
tREH
tCHZ tREA tCOH
tREA
tRHZ I/Ox tRR R/B
NOTES : Transition is measured at 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz.
tRHZ tRHOH
Dout
Dout
Dout
27
K9WAG08U1A K9K8G08U0A K9NBG08U5A
FLASH MEMORY
Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)
tRC tRP RE tREA tCEA I/Ox tRR R/B tREA tRLOH Dout tREH
CE
tCHZ tCOH
tRHZ tRHOH
Dout
NOTES : Transition is measured at 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz.
Status Read Cycle & EDC Status Read Cycle
tCLR CLE tCLS tCS CE tCH tCEA tWHR RE tDS I/Ox tDH tIR tREA tRHZ
tRHOH
tCLH
tWP WE
tCHZ tCOH
70h or 7Bh
Status Output
28
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Read Operation
tCLR CLE
FLASH MEMORY
CE tWC WE tWB tAR ALE tR RE tRR I/Ox
00h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
tRC
tRHZ
30h
tCHZ tCOH
Dout N+2
Dout N Dout N+1 Dout M
Column Address
Row Address Busy
R/B
Read Operation(Intercepted by CE)
CLE
CE
WE tWB tAR ALE tR RE tRR I/Ox
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h
tRC
Dout N
Dout N+1
Column Address
Row Address Busy
R/B
29
Random Data Output In a Page
CLE tCLR
K9WAG08U1A K9K8G08U0A K9NBG08U5A
CE
WE
tWB
tAR
tRHW
tWHR
30 tR
tRC
ALE tREA
RE tRR
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
I/Ox
Column Address Row Address Busy
00h
30h
Dout N
Dout N+1
05h
Col Add1
Col Add2
E0h
Dout M
Dout M+1
Column Address
FLASH MEMORY
R/B
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Page Program Operation
FLASH MEMORY
CLE
CE
WE tADL ALE tWB tPROG tWHR
RE
Din Din N M 1 up to m Byte Serial Input
I/Ox
80h
tWC
tWC
tWC
Co.l Add1 Col. Add2
Row Add1
Row Add2 Row Add3
10h Program Command
70h Read Status Command
I/O0
SerialData Column Address Input Command
Row Address
R/B
I/O0=0 Successful Program I/O0=1 Error in Program
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
31
Page Program Operation with Random Data Input
CLE
CE tWC
K9WAG08U1A K9K8G08U0A K9NBG08U5A
WE tADL tADL tWB
tWC tWC
tPROG
tWHR
ALE
RE
Serial Data Column Address Input Command Row Address
Serial Input Random Data Column Address Input Command
Serial Input
NOTES : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 2. For EDC operation, only one time random data input is possible at the same address.
32
Col. Add2 Row Add1 Row Add2 Row Add3
I/Ox
Col. Add1 Col. Add2
80h 85h
Col. Add1
Din N Din M
Din J
Din K
10h Program Command
70h Read Status Command
I/O0
R/B
FLASH MEMORY
Copy-Back Program Operation With Random Data Input
CLE
CE tWHR tPROG tWB tR tADL
K9WAG08U1A K9K8G08U0A K9NBG08U5A
tWC tWB
WE
ALE
Column Address Row Address Column Address
Row Address
Busy
Copy-Back Data Input Command
FLASH MEMORY
NOTES : 1. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 2. For EDC operation, only one time random data input is possible at the same address.
33
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
RE
I/Ox
35h
00h
85h
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
Data 1
Data N
10h
7Bh/70h
I/Ox Read EDC Status or Read Status Command
R/B
Busy
I/O0=0 Successful Program I/O0=1 Error in Program I/O1 ~ I/O2 : EDC Status (7Bh only)
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Block Erase Operation
FLASH MEMORY
CLE
CE tWC WE tWB ALE tBERS tWHR
RE I/Ox
60h
Row Add1
Row Add2 Row Add3
D0h
70h
I/O 0
Row Address
Auto Block Erase Setup Command
Erase Command
R/B
Busy
Read Status Command
I/O0=0 Successful Erase I/O0=1 Error in Erase
34
Two-Plane Page Program Operation
CLE
CE

tDBSY
tWC
WE
tWB tWB tPROG
tWHR
K9WAG08U1A K9K8G08U0A K9NBG08U5A
ALE
RE
I/Ox
80h
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
Din N 81h
Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
Din M
Din N
Din M
10h Program Confirm Command (True)
70h
I/O 0
Serial Data Column Address Input Command
11h Program Page Row Address 1 up to 2112 Byte Data Command (Dummy) Serial Input
Read Status Command
tDBSY :
typ. 500ns max. 1s
Ex.) Two-Plane Page Program tDBSY tPROG
R/B
80h Address & Data Input Col Add1,2 & Row Add 1,2,3 2112 Byte Data A0 ~ A11 : Valid A12 ~ A17 : Fixed 'Low' : Fixed 'Low' A18 A19 ~ A29 : Fixed 'Low' : Valid A30 11h
I/O0~7
Note
81h
Address & Data Input Col Add1,2 & Row Add 1,2,3 2112 Byte Data
10h
70h A0 ~ A11 : Valid A12 ~ A17 : Valid : Fixed 'High' A18 A19 ~ A29 : Valid A30 :Must be same as previous A30
35
R/B
FLASH MEMORY
Note: Any command between 11h and 81h is prohibited except 70h and FFh.
Two-Plane Block Erase Operation
CLE
CE tWC
tWC
WE tWB tBERS tWHR
K9WAG08U1A K9K8G08U0A K9NBG08U5A
ALE
RE
I/OX
60h
Row Add1 Row Add2 Row Add3
60h D0h Row Address Row Address
Row Add1 Row Add2 Row Add3 D0h
70h
I/O 0
36
Busy
Block Erase Setup Command2 Erase Confirm Command I/O 0 = 0 Successful Erase I/O 0 = 1 Error in Erase Read Status Command
R/B
Block Erase Setup Command1
* For Two-Plane Erase operation, Block address to be erased should be repeated before "D0H" command.
Ex.) Address Restriction for Two-Plane Block Erase Operation tBERS
Address 60h Row Add1,2,3 A12 ~ A17 : Fixed 'Low' : Fixed 'Low' A18 A19 ~ A29 : Fixed 'Low' A30 : Valid D0h ~ A25 A9Address Row Add1,2,3 A12 ~ A17 : Fixed 'Low' : Fixed 'High' A18 A19 ~ A29 : Valid A30 : Must be same as previous A30 D0h 70h
R/B
FLASH MEMORY
I/O0~7
60h
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Read ID Operation
FLASH MEMORY
CLE
CE
WE tAR
ALE
RE tREA I/Ox
90h Read ID Command 00h Address 1cycle ECh Device Code 3rd cyc. 4th cyc. 5th cyc.
Maker Code Device Code
Device K9K8G08U0A K9WAG08U1A K9NBG08U5A
Device Code(2nd Cycle) D3h
3rd Cycle 51h
4th Cycle 95h
5th Cycle 58h
Same as K9K8G08U0A in it
37
K9WAG08U1A K9K8G08U0A K9NBG08U5A
ID Definition Table 90 ID : Access command = 90H
Description 1 Byte 2nd Byte 3rd Byte 4th Byte 5th Byte
st
FLASH MEMORY
Maker Code Device Code Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size
3rd ID Data
Description 1 2 4 8 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Not Support Support Not Support Support 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 1 0 1 0 1
Internal Chip Number
Cell Type
Number of Simultaneously Programmed Pages Interleave Program Between multiple chips Cache Program
4th ID Data
Description Page Size (w/o redundant area ) 1KB 2KB 4KB 8KB 64KB 128KB 256KB 512KB 8 16 x8 x16 50ns/30ns 25ns Reserved Reserved 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 1 0 1 0 1
Block Size (w/o redundant area ) Redundant Area Size ( byte/512byte) Organization
Serial Access Minimum
38
K9WAG08U1A K9K8G08U0A K9NBG08U5A
5th ID Data
Description 1 2 4 8 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I/O7 I/O6 I/O5 I/O4
FLASH MEMORY
I/O3 I/O2 0 0 1 1 0 1 0 1
I/O1
I/O0
Plane Number
Plane Size (w/o redundant Area)
Reserved
0
0
39
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Device Operation
PAGE READ
FLASH MEMORY
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 20s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns(K9NBG08U5A:50ns) cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
ALE R/B RE I/Ox
00h
WE
CE
CLE
tR
Address(5Cycle) Col. Add.1,2 & Row Add.1,2,3
30h
Data Output(Serial Access)
Data Field
Spare Field
40
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Figure 7. Random Data Output In a Page
tR
FLASH MEMORY
R/B RE I/Ox
00h Address 5Cycles 30h
Data Output
05h
Address 2Cycles Col. Add.1,2
E0h
Data Output
Col. Add.1,2 & Row Add.1,2,3
Data Field
Spare Field
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
R/B I/Ox
80h Address & Data Input Col. Add.1,2 & Row Add.1,2,3 Data Fail
tPROG
"0" 10h 70h I/O0 "1" Pass
41
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Figure 9. Random Data Input In a Page
R/B I/Ox
80h Address & Data Input Col. Add.1,2 & Row Add1,2,3 Data Address & Data Input Col. Add.1,2 Data
FLASH MEMORY
tPROG
"0" 85h 10h 70h I/O0 "1" Fail Pass
Copy-Back Program
The Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copying-program with the address of destination page. A read operation with "35h" command and the address of the source page moves the whole 2,112-byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input command (85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actually begin the programming operation. During tPROG, the device executes EDC of itself. Once the program process starts, the Read Status Register command (70h) or Read EDC Status command (7Bh) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit(I/O 0) and EDC Status Bits (I/O 1 ~ I/O 2) may be checked(Figure 10 & Figure 11& Figure 12). The internal write verification detects only errors for "1"s that are not successfully programmed to "0"s and the internal EDC checks whether there is only 1-bit error for each 528-byte sector of the source page. More than 2-bit error detection is not available for each 528-byte sector. The command register remains in Read Status command mode or Read EDC Status command mode until another valid command is written to the command register. During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11. But EDC status Bits are not available during copy back for some bits or bytes modified by Random Data Input operation. However, in case of the 528 byte sector unit modification, EDC status bits are available.
Figure 10. Page Copy-Back Program Operation
R/B I/Ox
00h Add.(5Cycles) 35h
tR
tPROG
85h
Add.(5Cycles)
10h
70h/7Bh
I/O0 "1" Fail
"0"
Pass
Col. Add.1,2 & Row Add.1,2,3 Source Address
Col. Add.1,2 & Row Add.1,2,3 Destination Address
Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 2. On the same plane, It's prohibited to operate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages.
Figure 11. Page Copy-Back Program Operation with Random Data Input
R/B I/Ox
00h Add.(5Cycles) 35h
tR
tPROG
85h
Add.(5Cycles)
Data
85h
Add.(2Cycles) Col. Add.1,2
Data
10h
70h
Col. Add.1,2 & Row Add.1,2,3 Source Address
Col. Add.1,2 & Row Add.1,2,3 Destination Address
There is no limitation for the number of repetition.
Note: 1. For EDC operation, only one time random data input is possible at the same address.
42
K9WAG08U1A K9K8G08U0A K9NBG08U5A
EDC OPERATION
FLASH MEMORY
Note that for the user who use Copy-Back with EDC mode, only one time random data input is possible at the same address during Copy-Back program or page program mode. For the user who use Copy-Back without EDC, there is no limitation for the random data input at the same address.
Figure 12. Page Copy-Back Program Operation with EDC & Read EDC Status
R/B I/Ox
00h Add.(5Cycles) 35h
tR
tPROG
85h
Add.(5Cycles)
10h
7Bh
EDC Status Output
Col. Add.1,2 & Row Add.1,2,3 Source Address
Col. Add.1,2 & Row Add.1,2,3 Destination Address
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A18 to A30 is valid while A12 to A17 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
R/B I/Ox
60h
tBERS
"0" Address Input(3Cycle) Row Add 1,2,3 Fail D0h 70h I/O0 "1" Pass
Two-Plane Page Program
Two-Plane Page Program is an extension of Page Program, for a single plane with 2112 byte page registers. Since the device is equipped with four memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of two pages. But there is some restriction, two-plane program operations can be executed by dividing the memory array into plane 0~1 or plane 2~3 separately. For example, two-plane program operation into plane 0 and plane 2 is prohibited. That is to say, two-plane program operation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed. After writing the first set of data up to 2112 byte into the selected page register, Dummy Page Program command (11h) instead of actual Page Program command (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (70h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the 81h command and address sequences. After inputting data for the last plane, actual True Page Program(10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Althougth two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O 0 is set to "1" when any of the pages fails. Restriction in addressing with Two-Plane Page Program is shown is Figure14.
43
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Figure 14. Two-Plane Page Program
R/B I/O0 ~ 7 tDBSY
FLASH MEMORY
tPROG
80h
Address & Data Input A0 ~ A11 : Valid A12 ~ A17 : Fixed 'Low' A18 : Fixed 'Low' A19 ~ A29 : Fixed 'Low' A30 : Valid
11h
Note2
81h
Address & Data Input
10h
70h
A0 ~ A11 : Valid A12 ~ A17 : Valid A18 : Fixed 'High' A19 ~ A29 : Valid A30 : Must be same as previous A30
NOTE : 1. It is noticeable that same row address except for A18 is applied to the two blocks 2.Any command between 11h and 81h is prohibited except 70h and FFh. 80h 11h 81h 10h
Data Input
Plane 0 (2048 Block)
Plane 1 (2048 Block)
Block 0 Block 2
Block 1 Block 3
Block 4092 Block 4094
Block 4093 Block 4095
NOTE : It is an example for two-plane page program into plane 0~1(In this case, A30 is low), and the method for two-plane page program into plane 2 ~3 is same. two-plane page program into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited.
Two-Plane Block Erase
Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane. The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/ Busy status bit (I/O 6). Two-plane erase operations can be executed by dividing the memory array into plane 0~1 or plane 2~3 separately. For example, two-plane erase operation into plane 0 and plane 2 is prohibited. That is to say, two-plane erase operation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed.
Figure 15. Two-Plane Block Erase Operation
R/B I/OX
60h Address (3 Cycle) A12 ~ A17 : Fixed 'Low' :Fixed 'Low' A18 A19 ~ A29 : Fixed 'Low' A30 : Valid 60h Address (3 Cycle) D0h
tBERS
"0"
70h
I/O 0 "1" Fail
Pass
A12 ~ A17 : Fixed 'Low' : Fixed 'High' A18 A19 ~ A29 : valid A30 : must be same as previous A30 Must
NOTE : Two-plane block erase into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited.
44
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Two-Plane Copy-Back Program
FLASH MEMORY
Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2112 byte page registers. Since the device is equipped with four memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of two pages.
Figure 16. Two-Plane Copy-Back Program Operation
R/B I/Ox
00h Add.(5Cycles) 35h
tR
tR
00h
Add.(5Cycles)
35h
Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane0
Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane1
1
R/B I/Ox 1
Add.(5Cycles)
tDBSY
tPROG
85h
11h Note4
81h
Add.(5Cycles)
10h
70h
Col. Add.1,2 & Row Add.1,2,3 Destination Address A0 ~ A11 : Fixed 'Low' A12 ~ A17 : Fixed 'Low' A18 : Fixed 'Low' A19 ~ A29 : Fixed 'Low' A30 : Valid Plane0/2 Source page
Col. Add.1,2 & Row Add.1,2,3 Destination Address A0 ~ A11 : Fixed 'Low' A12 ~ A17 : Valid A18 : Fixed 'High' A19 ~ A29 : Valid A30 : Must be same as previous A30 Plane1/3
Source page Target page (1) (3) Target page (2) (3) (1) : Read for Copy Back On Plane0(or Plane2) (2) : Read for Copy Back On Plane1(or Plane3) (3) : Two-Plane Copy-Back Program
Data Field
Spare Field
Data Field
Spare Field
Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 2. On the same plane, It's prohibited to operate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages. 3. Two-plane copy-back page program into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited. 4. Any command between 11h and 81h is prohibited except 70h and FFh.
45
K9WAG08U1A K9K8G08U0A K9NBG08U5A
FLASH MEMORY
Figure 17. Two-Plane Copy-Back Program Operation with Random Data Input
R/B I/Ox
00h Add.(5Cycles) 35h
tR
tR
00h
Add.(5Cycles)
35h
Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane0
Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane1
1
tDBSY R/B I/Ox 1
85h Add.(5Cycles) Data 85h Add.(2Cycles) Col. Add.1,2 Data 11h Note4
Col. Add.1,2 & Row Add.1,2,3 Destination Address A0 ~ A11 : Valid A12 ~ A17 : Fixed 'Low' A18 : Fixed 'Low' A19 ~ A29 : Fixed 'Low' A30 : Valid
2
tPROG R/B I/Ox 2
81h Add.(5Cycles) Data 85h Add.(2Cycles) Col. Add.1,2 Data 10h
Col. Add.1,2 & Row Add.1,2,3 Destination Address A0 ~ A11 : Valid A12 ~ A17 : Valid A18 : Fixed 'High' A19 ~ A29 : Valid A30 : Must be same as previous A30
Note: 1. Copy-Back Program operation is allowed only within the same memory plane. 2. On the same plane, It's prohibited to operate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages. 3. EDC status Bits are not available during copy back for some bits or bytes modified by Random Data Input operation. In case of the 528 byte plane unit modification, EDC status bits are available. 4. Any command between 11h and 81h is prohibited except 70h and FFh.
46
K9WAG08U1A K9K8G08U0A K9NBG08U5A
READ STATUS
FLASH MEMORY
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 3 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles.
Table 3. Status Register Definition for 70h Command
I/O I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Page Program Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Block Erase Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Read Not use Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Pass : "0" Don't -cared Don't -cared Don't -cared Don't -cared Don't -cared Busy : "0" Protected : "0" Ready : "1" Not Protected : "1" Definition Fail : "1"
NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.
2. Status Register Definition for F1h & F2h command is same as that of 70h command.
READ EDC STATUS
Read EDC status operation is only available on 'Copy Back Program'. The device contains an EDC Status Register which may be read to find out whether there is error during 'Read for Copy Back'. After writing 7Bh command to the command register, a read cycle outputs the content of the EDC Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in EDC Status Read mode until further commands are issued to it.
Table 4. Status Register Definition for 7Bh Command
I/O I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 Copy Back Program Pass/Fail of Copy Back Program EDC Status Validity of EDC Status Not Use Not Use Not Use Ready/Busy of Copy Back Program Page Program Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Block Erase Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Read Not use Not use Not use Not Use Not Use Not Use Ready/Busy Definition Pass : "0", Fail : "1" No Error : "0", Error : "1" Valid : "1", Invalid : "0" Don't -cared Don't -cared Don't -cared Busy : "0", Ready : "1"
I/O 7 Write Protect of Copy Back Program
Write Protect Protected : "0", Not Protected :"1"
NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.
2. More than 2-bit error detection isn't available for each 528 Byte sector. That is to say, only 1-bit error detection is avaliable for each 528 Byte sector.
47
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Read ID
FLASH MEMORY
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation sequence.
Figure 18. Read ID Operation
CLE CE WE tAR ALE tWHR RE I/OX
90h 00h Address. 1cycle
tCLR tCEA
tREA
ECh
Device Code Device code
3rd Cyc.
4th Cyc.
5th Cyc.
Maker code
Device K9K8G08U0A K9WAG08U1A K9NBG08U5A
Device Code(2nd Cycle) D3h
3rd Cycle 51h
4th Cycle 95h
5th Cycle 58h
Same as K9K8G08U0A in it
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 19 below.
Figure 19. RESET Operation
R/B I/OX
FFh
tRST
Table 5. Device Status
After Power-up Operation mode 00h Command is latched After Reset Waiting for next command
48
K9WAG08U1A K9K8G08U0A K9NBG08U5A
READY/BUSY
FLASH MEMORY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig.20). Its value can be determined by the following guidance.
Rp VCC
ibusy 3.3V device - VOL : 0.4V, VOH : 2.4V Ready Vcc
R/B open drain output
VOH
CL
VOL Busy tf tr
GND Device
Figure 20. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25C , CL = 50pF
2.4 200
tr,tf [s]
150n
Ibusy
1.2 100 150
3m
Ibusy [A]
100n tr 50n
50 1.8 tf
0.8 0.6
2m 1m
1.8
1.8
1.8
1K
2K
3K Rp(ohm)
4K
Rp value guidance
Rp(min, 3.3V part) = VCC(Max.) - VOL(Max.) IOL + IL = 3.2V 8mA + IL
where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr
49
K9WAG08U1A K9K8G08U0A K9NBG08U5A
Data Protection & Power up sequence
FLASH MEMORY
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 100s is required before internal circuit gets ready for any command sequences as shown in Figure 21. The two step command sequence for program/erase provides additional software protection.
Figure 21. AC Waveforms for Power Transition
3.3V device : ~ 2.5V VCC High
3.3V device : ~ 2.5V
WP
WE
50
100s

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